Title :
Design of CMOS buffers using the settling time of the ground bounce voltage as a key parameter
Author :
Mejia-Motta, E. ; Sandoval-Ibarra, F. ; Santana, J.
Author_Institution :
CINVESTAV-Unidad Guadalajara, Mexico City, Mexico
Abstract :
Design guidelines for CMOS buffers using the settling time of the ground bounce as a key parameter are given. Special emphasis is made on calculating the package inductance by an effective, lumped, power supply bus parasitic inductance. A trade-off between driver geometry, power supply bus geometry and settling time power supply is obtained. Finally, this paper uses a macromodel for modeling the ground bounce produced by the buffer in the switching state
Keywords :
CMOS integrated circuits; buffer circuits; driver circuits; inductance; integrated circuit modelling; integrated circuit packaging; power supply circuits; CMOS buffers; bus geometry; driver geometry; ground bounce voltage; macromodel; package inductance; parasitic inductance; power supply bus; settling time; Circuit simulation; Driver circuits; Equations; Geometry; Inductance; MOSFETs; Power supplies; Switches; Timing; Voltage;
Conference_Titel :
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
Conference_Location :
Lansing, MI
Print_ISBN :
0-7803-6475-9
DOI :
10.1109/MWSCAS.2000.952857
