On-chip decoupling capacitor optimization using architectural level prediction

Switching generated supply grid noise presents a potential obstacle to the reduction of supply voltage and resulting power. This paper presents a novel design technique for sizing and placing on-chip decoupling capacitors based on current signatures from the microarchitecture. Simulation of a typical processor workload (SPEC95) provides a realistic stimulation of microarchitecture elements that is coupled with a spatial power grid model. Evaluation of this technique on a typical microprocessor implementation (Pentium II) indicates this technique can produce up to a 30% improvement in maximum noise levels over a uniform decoupling capacitor placement strategy