A pipelined digital frequency synthesizer based on feedback

Author

Palomäki, Kalle I. ; Niittylahti, Jarkko ; Lehtinen, Vesa

Author_Institution

Digital & Comput. Syst. Lab., Tampere Univ. of Technol., Finland

Volume

2

fYear

2000

fDate

2000

Firstpage

814

Abstract

In this paper, a fast, compact, and all-digital synthesizer capable of generating sine and cosine waveforms simultaneously is presented. The sinusoidal signal generation in the synthesizer is based on complex multiplication and feedback. A novel pipelined hardware architecture is presented. In addition to the general pipelining algorithm, simulation and synthesis results for a 16-bit signal synthesizer using a 0.35 μm 3.3 V 4-metal n-well standard cell CMOS-process are presented. The simulated maximum clock frequency of the 3-level pipelined synthesizer is 160 MHz. The estimated worst case spurious free dynamic range (SFDR) is 78 dBc

Keywords

CMOS digital integrated circuits; circuit feedback; direct digital synthesis; high-speed integrated circuits; pipeline arithmetic; waveform generators; 0.35 micron; 16 bit; 160 MHz; 3-level pipelined synthesizer; 3.3 V; complex multiplication; cosine waveforms; fast compact all-digital synthesizer; feedback; four metal n-well standard cell CMOS process; pipelined digital frequency synthesizer; pipelined hardware architecture; sine waveforms; sinusoidal signal generation; Clocks; Demodulation; Feedback; Frequency synthesizers; Hardware; Integrated circuit synthesis; Laboratories; Oscillators; Pipeline processing; Signal synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Conference_Location

Lansing, MI

Print_ISBN

0-7803-6475-9

Type

conf

DOI

10.1109/MWSCAS.2000.952880

Filename

952880