An optimized links-to-layout flow for timing critical designs

Author

Pallipatti, Sivakumar ; Ramabadran, Krishnan ; Ayathu, Sitharam

Author_Institution

Texas Instuments, Bangalore, India

Volume

2

fYear

2000

fDate

2000

Firstpage

970

Abstract

Timing closure flow for digital designs is referred to as links-to-layout (LTL) flow. The bottlenecks with this flow leads to non-optimal designs. Timing closure becomes totally unpredictable for complex designs and leads to significant increase in overall cost, in terms of die-area and time-to-market. Commercial tools to solve this problem are not yet fully proven and are also very expensive. An optimized LTL flow that addresses the timing and area problems was defined, implemented and verified. Significant improvements in design cycle time (60%-70%) coupled with excellent area gains (7-10%) were obtained using the optimized LTL flow

Keywords

circuit layout CAD; circuit optimisation; integrated circuit layout; logic CAD; timing; ISABEL; TVP6000; area gains; design cycle time; die-area; digital designs; optimized LTL flow; optimized links-to-layout flow; soft modem chip; time-to-market; timing closure; timing critical designs; video encoder chip; Clocks; Constraint optimization; Convergence; Cost function; Design optimization; Logic design; Modems; Process design; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Conference_Location

Lansing, MI

Print_ISBN

0-7803-6475-9

Type

conf

DOI

10.1109/MWSCAS.2000.952915

Filename

952915