A software LDPC decoder implemented on a many-core array of programmable processors

This paper presents the design and implementation of a software Low Density Parity Check (LDPC) decoder on the AsAP2 platform, which contains a 2D mesh of 164 programmable processors designed for general DSP applications. A software decoding algorithm is described which requires low memory overhead, and scalable methods are provided for parallelizing the computational workload across many cores. LDPC codes of length 4095 and 16129 are implemented, respectively using 152 or 156 processors, achieving 21.3 or 13.4 Mbps of throughput, and using 131 or 188 nJ per decoded bit over four decoding iterations.