• DocumentCode
    37557
  • Title

    CMOS Flat-Panel X-ray Detector With Dual-Gain Active Pixel Sensors and Column-Parallel Readout Circuits

  • Author

    Yun-Rae Jo ; Seong-Kwan Hong ; Oh-Kyong Kwon

  • Author_Institution
    Dept. of Electron. Eng., Hanyang Univ., Seoul, South Korea
  • Volume
    61
  • Issue
    5
  • fYear
    2014
  • fDate
    Oct. 2014
  • Firstpage
    2472
  • Lastpage
    2479
  • Abstract
    This paper proposes a CMOS flat-panel X-ray detector (FPXD) with dual-gain active pixel sensors (APSs) and column-parallel readout circuits to reduce the random noise. The proposed dual-gain APS employs the conversion gain control in a pixel sensor array and supports both high and low sensitivity modes for FPXD. The in-pixel conversion gain control suppresses the amplification of the pixel noise, so it improves signal-to-noise characteristics. The column-parallel readout circuits include single-slope analog-to-digital converters (SS-ADCs) and charge-summing circuits for pixel binning and analog double delta sampling (DDS). SS-ADCs support 12-bit resolution and use the driving method of gray-code counters with different initial values to reduce the peak current and the power fluctuation. They also employ a high resolution continuous-type ramp generator to reduce the area. The proposed CMOS FPXD with a pixel size of 100 μm × 100 μm was fabricated using a 0.18-μm CMOS process. The conversion gains in high and low sensitivity modes are designed with 0.43 μV/e- and 3.00 μV/e-, respectively. The measured random noises in high and low sensitivity modes are 366 μV and 400 μV, respectively, at the resolution of 12 bits and the frame rate of 30 fps. The area of ramp generator and the peak current of the gray-code counter are reduced by 92% and 43%, respectively, compared with the conventional structures.
  • Keywords
    CMOS integrated circuits; X-ray apparatus; X-ray detection; analogue-digital conversion; readout electronics; semiconductor counters; CMOS FPXD; CMOS flat panel X-ray detector; CMOS process; FPXD high sensitivity mode; FPXD low sensitivity mode; SS-ADC; analog DDS; charge summing circuits; column-parallel readout circuits; double delta sampling; driving method; dual gain APS; dual gain active pixel sensors; gray-code counters; high resolution continuous type ramp generator; high sensitivity modes; in pixel conversion gain control; low sensitivity modes; pixel binning; pixel noise amplification suppression; pixel sensor array; random noise; signal-noise characteristic improvement; single slope analog-digital converters; size 0.18 mum; size 100 mum; voltage 366 muV; voltage 400 muV; CMOS integrated circuits; Capacitance; Generators; Noise; Radiation detectors; Sensitivity; Timing; CMOS X-ray detector; column-parallel readout; dual-gain pixel; medical X-ray imaging; single-slope analog-to-digital converter (SS-ADC);
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.2014.2343459
  • Filename
    6880835