A low power radix-2 FFT accelerator for FPGA

This paper presents a low power FFT accelerator using a Radix-2 algorithm with an 8-parallel multi-path delay commutator. Hardware accelerators can achieve better performance and throughput compared to software FFT routines. Thus, FFT accelerators are used in many DSP processors. In this paper, a Radix-2 Multipath Delay Commutator (R2MDC) FFT accelerator is designed with 8-parallel processing of the input samples. The hardware utilization of the architecture is 100% requiring only 4 parallel butterflies. It increases the throughput to eight times that of the traditional R2MDC. Thus, it can achieve similar throughput while running at one eighth of the clock frequency for a regular MDC accelerator while roughly increasing the gate capacitance by 4 times. Thus, it can operate at a lower power than the regular Radix-2 MDC accelerator. We implement our design on the Xilinx Virtex FPGA and measure area, frequency, latency, throughput and power. We show that our design can operate at a similar rate while reducing the power by 25% on an FPGA compared to R2MDC.