DocumentCode
3755965
Title
The impact of faulty memory bit cells on the decoding of spatially-coupled LDPC codes
Author
Jiandong Mu;Aida Vosoughi;Joao Andrade;Alexios Balatsoukas-Stimming;Georgios Karakonstantis;Andreas Burg;Gabriel Falcao;Vitor Silva;Joseph R. Cavallaro
Author_Institution
Department of ECE, Rice Univ., Houston, TX, USA
fYear
2015
Firstpage
1627
Lastpage
1631
Abstract
In this paper, we investigate the decoding performance of spatially-coupled LDPC codes in the case of faulty memory bit-cells within the storage modules of the decoder. Our study characterizes error resilience, by measuring the BER degradation from such errors and we focus on the application of error mitigation techniques that further aid the inherent error resilience. In particular, we propose mitigation strategies based on the use of methods that consider the algorithmic significance of each bit-cell fault, such as MSB protection and self-correction of messages.
Keywords
"Decoding","Bit error rate","Parity check codes","Reliability","Circuit faults","Monte Carlo methods","Signal to noise ratio"
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 2015 49th Asilomar Conference on
Electronic_ISBN
1058-6393
Type
conf
DOI
10.1109/ACSSC.2015.7421423
Filename
7421423
Link To Document