• DocumentCode
    3756059
  • Title

    SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator

  • Author

    Chun-Hao Chang;Kuen-Wei Yeh;Jiun-Lang Huang;Laung-Terng Wang

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • fYear
    2015
  • Firstpage
    43
  • Lastpage
    48
  • Abstract
    Parallelism is one promising solution to accelerating the test pattern generation (TPG) process, several recent works also show that parallel TPG can reduce the test pattern count. However, today´s parallel TPG´s are mostly non-deterministic, i.e., the generated test set is timing and resource dependent, this complicates the debug process and may degrade the user experience. In this paper, we propose a multi-threading parallel test pattern generator that is both deterministic and incurs zero test inflation. Called SDC-TPG, the proposed parallel TPG relies on synchronized dynamic compaction (SDC) to generate the same test pattern set as the conventional serial TPG with dynamic compaction regardless of the thread timing and the thread count. Furthermore, an early primary fault TPG strategy is proposed to reduce the thread idle times and improve the speedup. Simulation results show that SDC-TPG achieves an average speedup of six with eight threads.
  • Keywords
    "Compaction","Instruction sets","Synchronization","Circuit faults","Test pattern generators","Simulation"
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium (ATS), 2015 IEEE 24th Asian
  • Electronic_ISBN
    2377-5386
  • Type

    conf

  • DOI
    10.1109/ATS.2015.15
  • Filename
    7422233