MPP Invited Speaker: Beyond von Neumann Architectures ? Dataflow, EDGE, and FPGAs

Summary form only given. The complete presentation was not made available for publication as part of the conference proceedings. The slowdown of conventional CPU scaling, predicted over a decade ago, has indeed come true. The shift to multicore provided some initial benefit, but scaling the number of cores has not provided the commensurate performance boost to keep pace with historic trends in CPU performance and efficiency. Dataflow and Explicit Dataflow Graph Execution (EDGE) architectures have the potential to provide a path forward for computer architecture scaling without radically altering silicon process technology, but programmability and a lack of available hardware have limited the impact that dataflow and EDGE have had. Field Programmable Gate Arrays (FPGAs) offer an interesting platform for bridging the gap between conventional von Neumann CPUs and dataflow/EDGE architectures. The programming model for FPGAs, at the core, is dataflow. With some minor modifications, this can become EDGE. This has the potential to solve the issue of hardware, and provides a viable platform for experimenting with dataflow and EDGE compilation and architectures. But FPGAs are far more than just a prototyping platform. In the datacenter, they are possibly the most powerful way of improving the performance and efficiency of cloud applications. At Microsoft, we developed Catapult, an FPGA platform customized to the datacenter, which provides enormous gains in performance and efficiency for datacenter workloads. This talk will discuss the Catapult platform, and the synergy between dataflow, EDGE, and the Catapult FPGA platform, and show the enormous potential that computer architects have to extend performance and efficiency in the face of slowing CPU scaling.