Title :
A Java processor architecture with bytecode folding and dynamic scheduling
Author :
El-Kharashi, M. Watheq ; Elguibaly, Fayez ; Li, Kin F.
Author_Institution :
Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada
Abstract :
This paper presents a novel processor architecture for executing Java bytecodes in hardware. Our processor is based on an instruction folding algorithm implemented with Tomasulo´s scheduling algorithm. The architecture also provides dual processing capability to execute Java bytecodes as well as other binaries. This approach improves Java execution without sacrificing the generality of the processor
Keywords :
Java; microprocessor chips; pipeline processing; virtual machines; Java bytecodes; Java execution; Java processor architecture; dual processing capability; instruction folding algorithm; reservation stations; scheduling algorithm; Computer architecture; Dynamic scheduling; Hardware; High level languages; Java; Microarchitecture; Pipelines; Scheduling algorithm; Software performance; Virtual machining;
Conference_Titel :
Communications, Computers and signal Processing, 2001. PACRIM. 2001 IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC
Print_ISBN :
0-7803-7080-5
DOI :
10.1109/PACRIM.2001.953584
