Effective Parallel Simulation of ArchHDL under Manycore Environment

For development of hardware such as System on a Chip (SoC), RTL simulation is very important to verify the design. Since RTL simulation has to be repeated many times during the development period, the simulation speed must be fast. However, as the design becomes larger and more complex, the simulation time dramatically increases and developers may not complete the simulation in a reasonable time. Therefore we have proposed a new hardware description language named ArchHDL which enables fast RTL simulation. Designers can write RTL design and test bench in a Verilog HDL-like style. Designers can compile design files in ArchHDL with standard C++ compiler and simulate them by executing the binary. The ArchHDL simulation is cycle accurate and can be parallelized using OpenMP without decreasing the accuracy. In this paper, we show the effectiveness of ArchHDL under a manycore environment. We use Intel Xeon Phi 31S1P Coprocessor in native execution mode to run parallel ArchHDL simulation. For performance evaluation, we use a NoC and a MIPS based manycore processor. As a result, the ArchHDL simulation on 57 cores of the Xeon Phi running at 1.1 GHz achieves up to 48x speedup compared to 1-core execution. Moreover, ArchHDL on 57 cores of the Xeon Phi is up to 9.7x faster than Synopsys VCS running on a single thread of Intel Xeon CPU E5-2687W operating at 3.1GHz and up to 1.7x faster than ArchHDL on 8 cores of the Xeon CPU E5-2687W.