DocumentCode :
3757610
Title :
FPGA Implementation of Modulo (231-1) Adder
Author :
R. D. Kharadkar;N. B. Hulle
Author_Institution :
Dept. of E&
fYear :
2015
Firstpage :
85
Lastpage :
90
Abstract :
Modulo (231-1) adder is one of the important module in ZUC stream cipher. The paper presents compact, high performance architecture for modulo (231-1) adder using CLA. The proposed architecture is implemented by using VHDL language with CAD tool Xilinx ISE Design Suite 13.2 and target device is Xilinx Spartan3-xc3s1000, with package FG320. Presented result shows that proposed architecture minimizes the chip area, power consumption and increases computation speed of modulo (231-1) adder.
Keywords :
"Mathematical model","Adders","Logic gates","Computer architecture","Delays","Ciphers","Silicon"
Publisher :
ieee
Conference_Titel :
Emerging Trends in Engineering and Technology (ICETET), 2015 7th International Conference on
Electronic_ISBN :
2157-0485
Type :
conf
DOI :
10.1109/ICETET.2015.23
Filename :
7425588
Link To Document :
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