DocumentCode :
3757915
Title :
Hard real-time bus architecture and arbitration algorithm based on AMBA
Author :
D.C Liang
Author_Institution :
College of Computer, National University of Defense Technology, Changsha 410073, China
fYear :
2015
fDate :
4/1/2015 12:00:00 AM
Firstpage :
1
Lastpage :
7
Abstract :
Real-time processors are growly used in embedded applications. Considering that the time cost in data transfer among devices is much more than the time used for computation and operation, it´s important to design a high-speed real-time bus structure in real-time systems. This paper offers a deep investigation to the characteristics of real-time systems as well as the basic structure of real-time processors and real-time buses. We designed a high-speed and time-predictable bus architecture called RTBus, where high-performance AXI protocol is employed. To accurately calculate the bus access time for master devices, a two-level real-time bus arbitration algorithm, which adopts the warning-line judgment mechanism and simulated annealing algorithm, is proposed for the operation of the RTBus. Finally, it is proved that RTBus provides a good solution to the conflicts when sharing resources in real-time processors.
Publisher :
iet
Conference_Titel :
Information and Communications Technologies (ICT 2015), 2015 International Conference on
Print_ISBN :
978-1-84919-994-0
Type :
conf
DOI :
10.1049/cp.2015.0235
Filename :
7426033
Link To Document :
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