FPGA implementation for GPR signal processing based on HW/SW co-design architecture

This paper proposes a field programmable gate array (FPGA) implementation for signal processing of a ground penetrating radar (GPR). The signal processing includes zero offset removal and clutter reduction. The implementation is based on the hardware and software (HW/SW) co-design. The hardware structures are introduced for performing zero offset removal and clutter reduction. The hardware structures are constructed with a basic processing elements such as multipliers and adders etc. Software designed on MicroBlaze is employed to control the hardware architectures and data flows including reading and writing memories. The design architectures including hardware and software is implemented on a Xilinx Zynq-7000 All Programmable SoC XC7Z020-CLG484-1 FPGA device. Experimental results based on the FPGA device are given to examine the performance of the proposed implementation. The B-scan GPR image are shown to demonstrate the ability of the proposed architecture. Preliminary experimentations show good agreement between implementation and simulation.