A dedicated analog digital converter for silicon photomultiplier readout

The analog digital converter (ADC) designed in UMC 0.18 μm CMOS technology is dedicated to the SiPM analog readout frontend “KLauS” developed before for the international linear collider (ILC) scintillator-based analog hadron calorimeter (AHCal). In order to make the carlorimeter as compact as possible, an extremly low power consumption is required by the AHCal such that active cooling can be avoided in the system. The upper limit of the power consumption is set to only 25 μW per channel with a 1% occupancy in the power pulsing mode. An 10-bit successive approximation register (SAR) structure is chosen for this application. The SAR structure with a capacitive digital-analog-converter (DAC) array promises a rather low power consumption. Moreover, a 10-bit resolution can be achieved without any digital calibration method and is sufficient for the minimum ionizing particle (MIP) response in the AHCal as well. For the special calibration mode of the AHCal operation, where SiPM single photon spectra are required for the pixel gain calculation, another pipelined stage can be attached to the SAR ADC such that a 12-bit resolution can be achieved. In addition to these, a peak-sensing track and hold unit is also implemented in front of the SAR ADC, the error for the self-held voltage is simulated to be less than 0.5 LSB in the 10-bit SAR ADC for an input voltage amplitude from 10 mV to 1 V. By using the peak-sensing method, the sampling frequency of the ADC is also reduced down to 2 MHz, which is still larger than the expected maximum event rate in the AHCal. The simulated DNL is less than 0.5 LSB in the worst case for the 10-bit SAR module and less than 0.3 LSB after calibration for the pipelined 12-bit module. The total power consumption of the nominal MIP operation mode is less than 600μW for an event rate of 2 MHz without any power pulsing techniques. The design details and the simulation results are presented.