Performance of a high-frequency synthesizable digitally-controlled oscillator

Phase-locked loops (PLLs) play a key role in electronic systems used in high energy physics experiments. They are often used as jitter cleaners or as a building blocks of high-speed serial transceivers deployed in trigger and data acquisition systems. A PLL includes analog sub-components and it generally requires to be implemented as a full custom block in an integrated circuit (IC). A technology upgrade implies a significant design effort for porting the PLL. In order to avoid this drawback, many digital solutions have been proposed for replacing the analog blocks and realize an All-Digital PLL (ADPLL). The main sub-component of an ADPLL is the digital controlled oscillator (DCO), which is often implemented by connecting a DAC to a voltage controlled oscillator. Unfortunately, this approach limits the overall portability of the design since the oscillator still remains a custom block. In this work, we present the performance of a DCO prototype implemented according to a truly all-digital, novel, technology-independent architecture. The architecture can be described by means of a hardware description language and it can be placed and routed with automatic place and route tools. These features make it possible to integrate our DCO in a pure digital design flow. Our solution is aimed at the use as a portable IP block in digital or mixed-signal ICs, however, as a proof-of-concept, we implemented our prototype in an Xilinx Kintex-7 FPGA. For this programmable device, our results show that the oscillator can reach a frequency range from 200 to 400 MHz and with an average least significant bit (LSB) of 21ps. We discuss the measured performance of our implementation in terms of output clock jitter, power consumption, frequency range, resolution, integral and differential non-linearity as a function of temperature, voltage and process.