Analysis and design considerations of static CMOS logics under process, voltage and temperature variation in UMC 0.18?m CMOS process

In this paper, we analyze the circuit characteristic of static CMOS logics and provide the size ratio of PMOS to NMOS transistors under process, voltage and temperature (PVT) variations in UMC 0.18 μm CMOS process. The threshold voltage of a MOS transistor is influenced seriously under PVT variations with different channel length setting. The performances of the static CMOS logics are unstable in ultralow voltage. To find the best size ratio of PMOS to NMOS transistors, NOT gate are simulated with various channel length setting and PVT conditions. Five stages of NOT gate are designed by different ratios respectively to compose the ring oscillator. By examining oscillator output frequency, then we analyze the change of current according to various channel length and PVT conditions. By further analyzing the simulation results, if the channel length of MOS transistors is shorter than 300nm, or the supply voltage is lower than 0.9 V, then the performance of MOS transistors is unstable in UMC 0.18 μm CMOS process. Through the data and the simulation provided by this paper, we can design the circuits with different needs, and we can also understand how each different section of PVT variations and channel length setting will affect the circuit in UMC 0.18 μm CMOS process.