Optimized VHDL-based Karatsuba polynomial multiplier generator for GF(2n)

Polynomial multiplication is the most significant operation in Elliptic Curve Cryptography (ECC). ECC is implemented in interactive application, which means the latency performance must obey some standards and constraints. When implemented in this kind of application, designer shouldn´t set the performance as fast as possible but just fast enough to preserve the application constrains so the area can be reduced. However, finding the best tradeoff between area/performance requires tedious and time consuming efforts. In this paper, we propose an autonomous method to find the most efficient area/performance trade-off for polynomial multiplication. First, it finds the least computational cost for polynomial multiplication using Karatsuba algorithm. Then, it would search the least area cost by sequencing the multiplication inside the karatsuba algorithm. Last, it would generate a VHDL code that ready to be used. This method is not only useful to find near optimal area/performance trade-off, but also it shortens the design cycle for embedded system design.