Temperature and time efficient parallel test scheduling for 3D stacked SoCs

Today´s VLSI circuits have improved immensely and have become very compact and complex. The advancements made are very fast and many designs and technologies have come up, System-in-a-package SiP, 3D-SoC, TSV based SoC to name a few. The complexity of circuits is increasing and with emphasis on less time to market, the number of defects and errors are increasing. This mandates a proper testing process to be adopted for all products. Testing is required to be performed on each manufactured product. At the same time it requires a low cost, highly efficient method to be adopted. It should involve good fault coverage, low cost and less time consuming. System on Chip is a design paradigm which involves integration of entire system onto a single chip. It can be a RAM, DRAM, CPU, UDL, analog, digital, A/D or D/A converters needed for any particular requirement. In this paper we have worked on test scheduling of 3D SoCs with thermal and time constraints. The circuits used have been built using benchmark SoC circuits taken from ITC´02 benchmark circuits. Various circuits have been stacked on top of each other for making 3D circuits. The method of test scheduling proposed has been compared with the sequential method of testing which involves testing of all cores of a SoC completely and then taking other circuit. The method proposed in this work gives good results and does not result in hotspot formation.