Clocked Adiabatic XOR and XNOR CMOS Gates Design Based on Graphene Nanoribbon Complementary Field Effect Transistors

In this paper, graphene nanoribbon field effect transistors (GNR FET) have been used in design of new energy-efficient XNOR/XOR gates based on clocked adiabatic logic (CAL), which results in the reduction of power density by nearly 65% comparing with the earlier CAL design in 45 nm technology node. In addition, the GNR FET allows scaling of supply voltage, which results in nearly three times reduction in power density. The on-chip power density of new XNOR/XOR gates remains below the limit reported by the International Technology Roadmap for Semiconductors (ITRS) up to the operation frequency of about 1GHz at the scaled supply voltage equal to 0.7V.