ZMesh: An Energy-Efficient Network-on-Chip Topology for Constant-Geometry Algorithms

This paper proposes an energy-efficient Network-on-Chip (NoC) topology called ZMesh, which is targeted towards the class of Constant-Geometry (CG) algorithms as well as generic traffic patterns. A simple technique has been followed to map functions to cores. The communication and traffic patterns of the considered algorithm class have been considered in synthesizing the proposed topology. The topology has been evaluated with the help of a cycle-accurate simulator for parameters such as area, power, and latency. Evaluation results show that the proposed topology has huge reduction in area at a nominal cost of latency when compared with DMesh, and better power-delay (latency) product when compared with several existing NoC topologies.