• DocumentCode
    3761706
  • Title

    Implementation of super-resolution algorithm on FPGA

  • Author

    Sharayu Hurdale;Prasad Khandekar

  • Author_Institution
    Dept. of Electronics & Tele Communication, Vishwakarma Institute of Information Technology, Pune, India
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    Super resolution technique gives an effective way to increase image resolution. Lower resolution is converted into higher resolution. By proposed super resolution algorithm, image is resolved sixteen times. This paper presents a FPGA (Field Programmable Gate Array) implementation of super resolution algorithm. FPGA is used because of its various advantages. In super resolution image size is increased by adopting information from input image itself. Using this algorithm image can be resolved up-to 2x, 4x, 8x and 16x.
  • Keywords
    "Field programmable gate arrays","Spatial resolution","Signal resolution","MATLAB","Real-time systems","Algorithm design and analysis"
  • Publisher
    ieee
  • Conference_Titel
    Computational Intelligence and Computing Research (ICCIC), 2015 IEEE International Conference on
  • Print_ISBN
    978-1-4799-7848-9
  • Type

    conf

  • DOI
    10.1109/ICCIC.2015.7435757
  • Filename
    7435757
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3761706