A sampling approach for efficient BEOL TDDB assessment

As semiconductor manufacturing process becomes increasingly complex in advanced technologies, time-to-fail characteristics of BEOL TDDB are often significantly affected by within-wafer process variations, especially in early development stages. With the presence of such an effect, an accurate estimation of TDDB model parameters becomes difficult and sometimes erroneous values can be observed, which may lead to an incorrect conclusion. In order to minimize an artifact of process variation effect on TDDB model parameters, we propose and demonstrate a practical approach of ramped-voltage sample screening followed by grouping of unstressed clone samples for TDDB stresses and determination of voltage stress sequence on samples with a dynamically generated stress wafermap instead of using a predetermined checkerboard pattern wafermap. It is also demonstrated that the proposed approach can help greatly improve the accuracy of long-term TDDB stress results, without invoking large sample studies. An example will be given with this sampling approach how a voltage acceleration parameter can be affected depending on the choice of samples.