• DocumentCode
    3762362
  • Title

    Aging model challenges in deeply scaled tri-gate technologies

  • Author

    S. Ramey;Y. Lu;I. Meric;S. Mudanai;S. Novak;C. Prasad;J. Hicks

  • Author_Institution
    Logic Technology Development Quality and Reliability, Design Technology Solutions, Intel Corp., Hillsboro, Oregon, U.S.A.
  • fYear
    2015
  • Firstpage
    56
  • Lastpage
    62
  • Abstract
    As tri-gate transistor technologies continue to scale to smaller dimensions, a variety of aging mechanisms become important to include in models to accurately predict end-of-life transistor performance. Traditional aging effects such as BTI and hot carrier continue to play a role. However, modeling these mechanisms becomes more complicated with the addition of recovery, variation, and local self-heating. Further, second-order effects are starting to accumulate, such as recovery interactions, minority carrier gate injection, damage localization, and interactions between hot carrier and BTI. This work highlights the roles and impacts of these various effects and how they will need to fit into a comprehensive aging model.
  • Keywords
    "Aging","Degradation","Logic gates","Hot carriers","Stress","Transistors","Integrated circuit modeling"
  • Publisher
    ieee
  • Conference_Titel
    Integrated Reliability Workshop (IIRW), 2015 IEEE International
  • Print_ISBN
    978-1-4673-7395-1
  • Electronic_ISBN
    2374-8036
  • Type

    conf

  • DOI
    10.1109/IIRW.2015.7437067
  • Filename
    7437067