Title :
Wafer level test arrays with simple BIST to expedite process development for circuit reliability
Author :
M.-H. Hsieh;T.-Y. Yew;Y.-C. Huang;Y.C. Wang;W. Wang;Y.-H. Lee;J.H. Lee
Author_Institution :
TQRD, Taiwan Semiconductor Manufacturing Company, 121, Park Ave. 3, Hsinchu Science Park, Taiwan 30077
Abstract :
Conventional time consuming methodology and idealistic stress conditions are no longer satisfactory under fierce competition between advanced technology development approaches. In this paper, the effectiveness of test arrays with simple built-in self-test (BIST) design in FinFET high-k/metal gate (HK/MG) technology have been demonstrated through three experiments performed early in the process development cycle, before products were available to drive yield and process improvements. Early warnings of potential circuit level quality and reliability risk could save several major detours for technology advancement.
Keywords :
"Stress","Integrated circuit reliability","Delays","Built-in self-test","Sensors","Electrical resistance measurement"
Conference_Titel :
Integrated Reliability Workshop (IIRW), 2015 IEEE International
Print_ISBN :
978-1-4673-7395-1
Electronic_ISBN :
2374-8036
DOI :
10.1109/IIRW.2015.7437072
