AgELESS: Aging estimation and lifetime enhancement in silicon systems

While there has been tremendous progress in understanding reliability mechanisms at the level of individual devices and wires, circuit designers have traditionally used little of this information. By understanding aging mechanisms and percolating aging information to all levels of design abstraction, functional and reliable chips may be built using an aging-aware design methodology that is scalable to the full-chip level. This talk will illustrate techniques used to estimate and enhance the reliability of large digital circuits under the AgELESS project. Practical solutions for analyzing and improving the lifetime of a design, both during the design stage and when the chip is in the field, will be illustrated.