DocumentCode :
3762828
Title :
Reducing the number of embedded multipliers in squaring large size complex numbers
Author :
Fatima-Ezzahra Guessous;Noureddine Chabini
Author_Institution :
Web Help Company, Rabat, Morocco
fYear :
2015
Firstpage :
25
Lastpage :
26
Abstract :
To square large size complex numbers using n×n embedded multipliers as in using FPGAs, one needs to first partition the real and imaginary parts into segments of size less or equal to n and then to multiply the segments using these embedded multipliers. When the size of some segments is small, we show that three multiplications can be carried out using one n×n multiplier thus two n×n embedded multipliers can be saved. The idea is also applicable in carrying out two small squarers using one n×n embedded multiplier.
Keywords :
"Field programmable gate arrays","Image segmentation","Computers","Companies","Digital signal processing","Digital images","Signal processing algorithms"
Publisher :
ieee
Conference_Titel :
Microelectronics (ICM), 2015 27th International Conference on
Electronic_ISBN :
2159-1679
Type :
conf
DOI :
10.1109/ICM.2015.7437978
Filename :
7437978
Link To Document :
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