Implementation of a 17 bits Pulse Width Modulation circuit using FPGA

This paper presents the implementation of a 17 bits digital pulse width modulator (DPWM). Smaller pulses were obtained using internal carry chains that are available in many FPGAs. Our proposed architecture minimizes the critical paths that influence the linearity and induces the creation of carry chains without the use of adders. The frequency of the DPWM is 90.5kHz with a resolution of approximately 80ps, and the clock frequency is 46.34MHz.