An analytical Nanowire Tunnel FET (NW-TFET) model with high-k dielectric to improve the electrostatic performance

This work presents both the analytical and simulation study of electrostatic performance for high-k dielectric (Si3N4) based Nanowire Tunnel FET. The analytical drain current for the model has been developed using minimum tunneling length and lateral electric field. The analysis is extended to measure the electrostatic parameters such as surface potential, electric field, and minimum tunneling distance and the results are compared with conventional low-k dielectric (SiO2) based model. It has been revealed that the high-k dielectric improves the drain current and reduces the threshold potential in the ON-condition. But the device produces large leakage current at OFF-state. The compared results have been authenticated using TCAD Sentaurus device simulator.