AES implementation on Xilinx FPGAs suitable for FPGA based WBSNs

The Advanced Encryption Standard (AES) is a symmetric key Block cipher that is used to provide data confidentiality in many embedded systems. Data confidentiality of each information is very important, either the information is related with bank account statements, credit card numbers, trade secrets, government documents or personal information. The confidentiality of a patient´s physiological data is an important issue in traditional wireless body sensor networks (WBSNs) due to the limited hardware resources, which makes traditional WBSNs not suitable for the implementation of security mechanisms. The Xilinx FPGAs (Field Programmable Gate Arrays) is a suitable option for FPGA based WBSNs, because of the availability of more logic resources and better performance of FPGA. In this paper an FPGA based WBSN approach is discussed and an efficient implementation of AES is provided on latest Xilinx FPGAs (Artix-7, Virtex-7, Virtex-6, Virtex-4 and Spartan-6) that can be used to provide data confidentiality in FPGA based WBSNs. The presented efficient implementation technique of AES uses Block RAM resources of FPGA to get an optimized architecture with respect to power, speed and area. The results are provided in terms of throughput, slices, TPA and power. The XPA (Xilinx Power Analyzer) tool of Xilinx is used for power analysis.