• DocumentCode
    3763438
  • Title

    Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology

  • Author

    Chun-Yu Lin;Ming-Dou Ker;Pin-Hsin Chang;Wen-Tai Wang

  • Author_Institution
    Department of Electrical Engineering, National Taiwan Normal University, Taiwan
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    To protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.
  • Keywords
    "Electrostatic discharges","Thyristors","Logic gates","CMOS integrated circuits","Robustness","Voltage measurement","High K dielectric materials"
  • Publisher
    ieee
  • Conference_Titel
    Nanotechnology Materials and Devices Conference (NMDC), 2015 IEEE
  • Type

    conf

  • DOI
    10.1109/NMDC.2015.7439250
  • Filename
    7439250
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3763438