• DocumentCode
    3763781
  • Title

    An ultra-low-voltage, semi-floating-gate, domino, dual-rail, NOR gate

  • Author

    Ali Dadashi;Omid Mirmotahari;Yngvar Berg

  • Author_Institution
    Nanoelectronics Research Group, Department of Informatics, University Of Oslo, Oslo, Norway
  • fYear
    2015
  • Firstpage
    61
  • Lastpage
    64
  • Abstract
    In this paper, a new ultra low voltage (ULV) dual-rail NOR gate based on the semi-floating-gate (SFG) structure is presented. Higher speed in the lower supply voltages and robustness against process variations, are the main advantages of the proposed approach in comparison to the previously reported domino dual-rail NOR gate. The simulation results in a typical TSMC 90nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.
  • Keywords
    "Logic gates","Transistors","CMOS integrated circuits","Simulation","Inverters","Robustness","Threshold voltage"
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits, and Systems (ICECS), 2015 IEEE International Conference on
  • Type

    conf

  • DOI
    10.1109/ICECS.2015.7440249
  • Filename
    7440249
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3763781