A tool for transient fault analysis in combinational circuits

With technology downscaling, the vulnerability of combinational logic circuits to transient faults has increased resulting in error rates approaching those of memories. Thus, to guarantee a good use of selective hardening techniques, fast and accurate approaches for transient fault analysis in logic circuits are needed. In this work, we describe a methodology for Soft Error Rate (SER) evaluation in combinational logic circuits that manages the dependency of logical and electrical masking effects in case of reconvergent fanouts. The approach combines analytical transient fault propagation model and fault simulation to speed up simulations.