Impact on performance, power, area and wirelength using electromigration-aware cells

Electromigration (EM) is one of the critical reliability concerns, causing shorts and opens in metal interconnects, leading to interconnection failures and decreasing the time to failure (TTF) of the chip. In this way, EM-aware optimization is an important step of high reliability circuit design. Usually EM optimizations are applied on the power network and signals connecting cells. Otherwise, the internal wires of the cells are also affected by EM and they also have to be optimized to be EM-aware. One way to reduce the EM effects inside of the cells is placing the output pins at positions that reduce the EM. The critical pin positions that produces high current densities and consequently more EM are avoided, making the cells EM-aware. Thereby, in this work we are presenting the impact on area, delay, power and wirelength when different amounts of cells in a circuit are optimized to be EM-aware. We are using the NANGATE 45nm cell library scaling down to 22nm considering SPICE PTM models for simulation.