Automatic circuit generation for sequential logic debug

Integrated circuits (ICs) evolution follows a complex scaling process and an increasing number of transistors per chip. As feature sizes reduces, logic gates get more susceptible to manufacturing and specification errors, which makes testing an important step in their design. The early on-silicon validation of the logic functionality is very important to reduce the time-to-market and the cost of faults in new standard cell libraries. This paper presents a procedure for automatic generation of on-chip self-testers for complete logical debug of any sequential gate. All shorted and open interconnects, short-to-power, short-to-ground, stuck-open, and stuck-on faults can be detected. The analysis compares the complexity of the generated validation circuits for different latches and flip-flops. Logic and physical synthesis were performed to generate the circuit layouts and confirm its practical usability.