Performance evaluation of dynamic partial reconfiguration techniques for software defined radio implementation on FPGA

Reconfigurability of SRAM-based Field Programmable Gate Arrays (FPGAs) is the most powerful feature over ASIC designs. Dynamic Partial Reconfiguration (DPR) emphasizes this feature by adding more flexibility over runtime phase. Xilinx Virtex family of FPGAs provides four techniques to perform DPR; SelectMAP, Serial mode, JTAG, and ICAP. In this paper, each of these techniques is reviewed, evaluated, and tested using Convolutional encoder, an essential block from Software Defined Radio (SDR) system, which becomes the most promising application for DPR. Experiments are carried out using Xilinx Virtex 5 kit "XUPV5-LX110T" to measure the trade-offs between performance and area-overhead by adding reconfiguration controller on/off FPGA fabric. It is shown that the performance of each interface is independent of design resource, but proportional only with partial reconfiguration region selection that had been chosen at design place and route phase.