An 8kb SRAM macro in 65nm for ultra-low voltage applications operating from 1.2V to 0.5V

Low-voltage operation for SRAM memories is attractive because it decreases leakage and active power. Hence, energy constrained applications, where performance requirements are not aggressive benefit significantly from an SRAM that offers read and write functionality at the lowest possible supply voltage. This paper explores the limits of low-voltage operation for traditional SRAM and periphery circuits. Read and Write assist techniques are implemented to reach such a low voltage with a 6T bitcell. A test macro of 8-Kbit is designed in 65nm CMOS technology. Simulations show that the design is capable of working down to 0.5V with a frequency of 380-KHz at the worst process corner.