Coupling capacitance extraction in through-silicon via (TSV) arrays

In this paper, we discuss a well known modeling approach that is used to extract the coupling capacitance between any two neighboring through silicon-vias (TSVs) in three dimensional integrated circuits (3D-ICs). This model has been used by many publications due to its modularity, easiness and quick turnaround time. However, the model is based on a homogeneous surrounding medium assumption. Our work shows that the homogeneous medium assumption is inaccurate due to the fact that each TSV is actually surrounded by a non homogeneous medium (silicon and silicon dioxide materials). The theory behind this claim is provided and validated using quasi static field solver simulations (ANSYS Q3D). The percentage error in coupling capacitance between Q3D extraction results and the homogeneous medium model results can reach 70%. We suggest alternative modeling approaches that can provide better accuracy with emphasizing the pros and cons of each approach.