A new 16-bit low-power PVT-calibrated time-based differential Analog-to-Digital Converter (ADC) circuit in CMOS 65nm technology

Time-Based Analog-to-Digital Converter (ADC) becomes the key of the new era of scaling CMOS technology. It provides a lower power and area than conventional ADCs. These improvements urges the Time-Based ADC to overcome Software Defined Radio (SDR) receivers´ challenges and to be a dominant module in designing them. Such an SDR receiver can adapt itself automatically to deal with the desired bandwidth. This permits more technologies to be built-in the same single chip. Time-Based ADC includes a Voltage-to-Time Converter (VTC) and a Time-to-Digital Converter (TDC). In this work, we present a novel differential VTC simulated under process-voltage-temperature (PVT) variations using TSMC 65nm CMOS technology. It is connected with a TDC algorithm implemented on MATLAB to form a complete ADC. The proposed ADC is based on a new design methodology which reports at higher input frequencies after calibration a higher Effective-Number-of-Bits (ENOB) than previously published ADC circuits in TSMC 65nm CMOS technology, with a supply voltage of 1.2V.