A low-power high-speed charge-steering ADC-based equalizer for serial links

This paper presents a 20-GSps low-power ADC-based equalizer for high speed serial links receiver. Digital receivers are recently adopted to overcome the challenges of power, delay and mismatches facing circuits in the analog domain besides utilizing benefits of the digital domain of scaling, adaptation algorithms, calibration and noise immunity. The ADC-based equalizer is designed and simulated in a 65-nm CMOS technology and dissipates 15.5 mW in the ADC and 0.45 mW in the discrete-time linear equalizer from 1-V supply. Low power consumption is achieved by using interleaving in ADC architecture, utilizing charge-steering concept, sharing single reference ladder across the four interleaved branches of ADC, and using a novel proposed design for the comparator itself in the Flash ADC besides using the novel Discrete Time Linear Equalizer-DTLE-circuit.