Title :
Speeding-up fast fourier transform
Author :
Mohammed A. El-Motaz;Ahmed M. El-Shafiey;Mohamed E. Farag;Omar A. Nasr;Hossam A. H. Fahmy
Author_Institution :
Department of Electronics and Electrical Communication Engineering, Cairo University, Giza, Egypt
Abstract :
This work proposes a restructure of FFT algorithm to be more hardware friendly. The proposed algorithm is modeled as a combinatorial optimization problem. This paper presents two sub-optimal schemes of the proposed FFT restructure: one-stage and two-stage optimization. The proposed FFT algorithm is applied on 1024-point Radix-2 Single-Path Delay Feedback (R2SDF) architecture. The one-stage and two-stage optimization schemes achieve reduction in the multipliers area by 40.8% and 62.5%, respectively, compared with the conventional algorithm.
Keywords :
"Optimization","Hardware","Signal processing algorithms","Computer architecture","Fast Fourier transforms","Delays","Pipelines"
Conference_Titel :
Electronics, Circuits, and Systems (ICECS), 2015 IEEE International Conference on
DOI :
10.1109/ICECS.2015.7440365