Yield optimization of spintronic memristor-based memory arrays

The missing fourth passive essential circuit element-memristor enticed a big attention after HP labs evolved the first memristor device in 2008. Aside from the solid-state thin film memristor device, spintronic memristor was also feigned based on the magnetic technology. As it is at nano-scale geometry size, the memristor device suffers from the process variations in the fabrication process. Process variations swerve the actual electrical behavior of memristors from the desired values. This deviation results reduce the yield particularly in the memristor-based memory design. Therefore, it is serious to understand and distinguish the impact of process variations on memristor performance and yield and attempt to optimize the yield of the spintronic memristor-based memory arrays. In this paper, we describe a compact model of the spintronic memristor based on the magnetic-domain-wall motion mechanism.