A variable interval enhanced jitter tolerant programmable bandwidth blind-oversampling CDR for multi-gigabit rates

An enhanced jitter tolerant programmable blind-oversampling clock and data recovery circuit (CDR) is presented. The clock´s sampling edge is ensured to be at the mid-position of the two data edges abounding the current bit. Clock position in the n´th UI (unit interval) is a function of position of the imminent data edges surrounding the n´th UI and previous (n-2) data edges with programmable weights. To ensure causality of system a calibrated delay line with two degrees of freedom is placed in the data path. The output clock acquisition happens in two stages namely the coarse acquisition through the blind-oversampling scheme followed by the fine acquisition through a delay locked loop. In oversampling circuit the acquired phase of the clock aligns with a coarse resolution towards the bit centre with a very low latency. The output clock of the oversampling circuit is used in a BBPD to form a delay locked loop (DLL) with the calibrated delay chain in the data path for tracking the bit centre with a very high resolution. Modelling and simulation results indicate a higher jitter tolerance of the derived clock in contrast with the state of art clock recovery circuits.