Area efficient and high throughput CABAC encoder architecture for HEVC

The rising of High Efficiency Video Coding (HEVC) standard in the last years to encode Ultra High Definition (UHD) resolution videos bring challenges to both algorithmic and hardware solutions. The entropy encoder, Context-adaptive binary arithmetic coding (CABAC), presents difficulties to parallelize as well as pipelined with effectiveness. This occurs due to data dependencies in its algorithm. This paper presents an area efficient architecture to deliver the throughput required by CABAC encoding for UHD content. To meet this requirement, we propose optimizations in the renormalization exploiting parallelism, and, we improve the binary arithmetic encoding (BAE) by reducing the critical path delay while increasing the throughput. This technique increases the bins per clock cycle to an average of 2.37. Moreover, simulation results show that our architecture can work at 380MHz with 31.180K gates targeting 0.13μm CMOS process. These results endure support for real-time encoding for all sequences under common test conditions (CTC) of HEVC standard conforming to the main profile.