Gaussian random number generator design based on double non-uniform segmentation

This paper presents a new approach to design a Gaussian variate generator (GVG) circuit, based on the Box-Muller algorithm. The proposed GVG utilizes a double non-uniform segmentation combined with the use of CORDIC algorithm to reduce the block memory and to remove the hardware multipliers, respectively. These modifications result in a compact hardware which has a reduced resources occupation and generate a higher tail accuracy of. An implementation on a XILINX Virtex-5 xc5vfx130tff1738-2 FPGA occupies 705 slices, 1 block RAM and generating 380 million samples per seconde at a clock speed of 190 MHz.