An FPGA-based accelerator for rapid simulation of SC decoding of polar codes

In this paper we present an FPGA-based system for rapid frame error rate simulations of successive cancellation decoding of polar codes. Our system is implemented on a Xilinx Virtex-7 XC7VX485T FPGA and it supports polar codes of any rate and of blocklength up to N = 1024 bits on that device. The supported simulation speed with N = 1024 is 108 codewords per second at a frequency of 100 MHz. The key idea that enables this high throughput is that the feedback part of the successive cancellation decoder can be ignored when evaluating the frame error rate. Thus, we can implement a heavily parallelized and deeply pipelined SC decoder which can output one decoded codeword per cycle. Moreover, the random input required to perform Monte Carlo simulations of the decoder is generated on-chip by means of free-running XOR-based true random number generators at a rate of approximately 1 Terasamples per second.