Topological constraints of gate-level circuits obtained through standard cell recognition (SCR)

This paper presents topological constraints of gate-level circuits obtained through standard cell recognition applied to gate-level commercial microelectronics verification. A suite of topological constraints, including the gate vertex count, net vertex count, terminal count, blocks, circuit genus, Euler characteristic, and number of faces are extracted from gate-level circuits obtained through standard cell recognition. Topological constraints are computed for two full adder cells at fourth level of abstraction and for two full adder cells at the third level of abstraction. Two mathematical frameworks are also introduced to describe physically distinct situations in hardware that are represented in a schematic as functionally equivalent. The first method uses the concept of a braid word, and the second method uses the concept of a crossing vertex. Schematic braid words corresponding to each of two full adder cell schematics at fourth level of abstraction and for two full adder cell schematics at the third level of abstraction are derived. Chip braid words corresponding to the set of unique physical designs that could potentially be realized in chip hardware from a schematic are obtained and discussed. Potential capabilities of these approaches for gate-level circuits are discussed.