A hardware implementation of an orthorectification process

This paper presents a hardware implementation of an image orthorectification process using the back-projection algorithm. Image orthorectification is integral to effective analysis and exploitation of aerial imagery and is often one of the largest processing bottlenecks. As imaging sensors grow in pixel count and associated target footprint, the image orthorectification process requires an associated increase in compute capability. In order to support size, weight, and power (SWaP) constrained processing environments, such as on-board systems for unmanned aerial vehicles (UAVs), efficient and scalable solutions must be developed. Moreover, in surveillance applications minimizing latency is paramount. This paper presents an integer-based high performance FPGA implementation of a back-projection algorithm for orthorectification. A 2.4x speedup is achieved over software processing with an associated 15x reduction in total power draw.