• DocumentCode
    3764559
  • Title

    An output capacitor-less cascode flipped voltage follower based low dropout regulator

  • Author

    Pratibha Kumari;Gangasagar Panuganti;Suresh Alapati;Sreehari Rao Patri

  • Author_Institution
    Department of ECE, National Institute of Technology, Warangal, India - 506004
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In this paper, a multi feedback loop, output capacitor-less LDO is proposed. The proposed LDO uses an adaptively biased folded cascode error amplifier and cascode flipped voltage follower (FVF) at the output. The LDO is designed in UMC 180nm technology, with an input voltage of 1.8V and a regulated output voltage of 1.6V. The LDO achieves a load regulation to an accuracy of 0.059V/A; the undershoot and overshoot of 100mV and 76mV, respectively for a load current step of 0 - 100mA, with rise/fall time of 500ns, within a settling time of 730ns. Contrary to Miller frequency compensation, indirect frequency compensation with split transistors is used. A total compensation capacitance of 6.7pF is used to achieve stability. The LDO consumes a total quiescent current of 61uA.
  • Keywords
    "Logic gates","Transistors"
  • Publisher
    ieee
  • Conference_Titel
    India Conference (INDICON), 2015 Annual IEEE
  • Electronic_ISBN
    2325-9418
  • Type

    conf

  • DOI
    10.1109/INDICON.2015.7443257
  • Filename
    7443257